FOROXSWITCH

Reliability of ultrathin high-K dielectrics for ADVanced MOS transistors

 

Research Partners: Universidad Autónoma de Barcelona & Tokio Institute of Technology (Japan)

Funding Agency / Institution: AGAUR. Generalitat de Catalunya.

Period: 2 years (1/1/2011-31/12/2012)

Project coordinator: Enrique Miranda (UAB) & Hiroshi Iwai (TIT)

Research team members:  Enrique Miranda, Jordi Suñé, C. Dou, S. Kano, K. Kakushima, T. Kawanago, H. Iwai

Total funding:  31.727,52€


 

Project objectives

Even if other possible electron devices have been considered as an alternative for the electronics of the nanoscale era, there is wide consensus that the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is still the best positioned candidate to build the nanoelectronics circuits of the near and mid-term future. Significant advances have been accomplished to the date in the fields of single electron tunneling, intramolecular conduction, carbon nanotubes, spintronics, etc., but operative devices based on such mechanisms suitable for large scale integration are still in an early development phase. Although the physical principles as well as the basic structure of the MOSFET have remained essentially unaltered since its origin, the performance of devices and circuits have largely improved within the last decade mainly because of a redesign strategy based on aggressive dimensional scaling. However Si-based technologies are approaching their physical limits, and technology breakthroughs, in terms of materials and processes, will be required as device sizes reach the nanoscale frontier. This rapid shrinking of the transistor feature size has forced the channel length and gate dielectric thickness to also decrease rapidly because of well-defined scaling rules. Alternative gate insulators with higher electrical permittivity (high-K) than silicon dioxide (SiO2, K=3.9) are currently under investigation to allow the scaling of CMOS technologies to minimum feature sizes of 45 nm and below. However, although the idea of substituting materials seems to be straightforward and simple, the current lack of understanding relating to the origin and control of defect states in the bulk and at the high-K/semiconductor interface as well as the lack of knowledge about the long-term stability of these states on the behaviour of the devices are some of the primary obstacles to the successful incorporation of high-Ks into mainstream semiconductor processes.

 

In this project, the attention will be mainly focused on the reliability aspects of high-K materials from the metal oxide groups IVB and IIIB such as hafnium dioxide (HfO2, K=23) and lanthanum oxide (La2O3, K=27). These dielectrics have shown much promise in overall materials properties as candidates to replace SiO2. However, a major problem is that these high-K layers when deposited directly on the silicon surface are known to give rise to severe mobility degradation and threshold voltage instability as compared to thermal SiO2. By investigating the leakage current through the gate insulator and the channel current in MOS transistors we expect to gain new insights into the degradation mechanisms that lead to the dielectric breakdown of the referred materials.

 

Results/Publications

E. Miranda, S. Kano, C. Dou, K. Kakushima, J. Suñé and H. Iwai

Nonlinear conductance quantization effects in CeOx/SiO2-based resistive switching devices

Applied Physics Letters vol. 101, 012910 (2012)

E. Miranda, T. Kawanago, K. Kakushima, J. Suñé, and H. Iwai

Analysis and modeling of the gate leakage current in advanced on MOSFET devices with severe gate-to-drain dielectric breakdown

Microelectronics Reliability, vol. 52 ,1909 (2012)

E. Miranda, T. Kawanago, K. Kakushima, J. Suñé, H. Iwai,

Modeling of the output characteristics of advanced n-MOSFETs after a severe gate-to-channel dielectric breakdown

Microelectronics Engineering, vol. 109, 322-325 (2013).

E. Miranda, T. Kawanago, Takamasa, K. Kakushima, J. Suñé, H. Iwai,

Analysis and Simulation of the Postbreakdown I-V Characteristics of n-MOS Transistors in the Linear Response Regime

IEEE Elect. Dev. Lett., vol. 34, 798-800 (2013)

E. Miranda, S. Kano, C. Dou, J. Suñe, H. Iwai

Effect of an ultrathin SiO2 interfacial layer on the hysteretic current-voltage characteristics of CeOx-based MIM structures Thin Solid Films, vol. 533, 38-42 (2013)